In this specification, the term integrated circuit is used to describe a chip or MCM (multi-chip module) embedded with DFT (design-for-test) techniques.
An integrated circuit generally contains multiple clock domains, with each clock domain being driven by a clock, which is either generated internally or supplied externally. Each clock domain further consists of a set of storage elements. Each clock is distributed to the set of storage elements belonging to the same clock domain via a skew-minimized network, which supplies clock pulses to all clock domain storage elements essentially at the same time. While the clock skew within a single clock domain is designed to be negligible, the clock skew between different clock domains can vary greatly for storage elements belonging to different clock domains. Two different types of combinational logic can be distinguished in an integrated circuit containing multiple clock domains. The first is intra-clock-domain combinational logic, which originates and terminates within the same clock domain. The second is inter-clock-domain combinational logic, which originates in one clock domain and terminates in a different clock domain.
Scan-based design is the most widely used design-for-test (DFT) approach for producing high-quality integrated circuits. Scan-based design requires that all storage elements in an integrated circuit, such as D flip-flops, be replaced with their scan-equivalent storage elements, such as Scan D flip-flops, otherwise known as scan cells. These scan cells are connected in such a way as to form one or more scan chains, with each scan chain being controlled by one or more scan enable (SE) signals and one or more clocks, each belonging to a different clock domain.
Testing a scan-based integrated circuit proceeds in a sequence of shift-in/shift-out operations and capture operations, which are repeated for a predetermined number of test patterns. During a shift operation, the scan enable (SE) signals are used to configure the scan cells into scan chains by selecting the scan data input as the input source for all scan cells in the scan-based integrated circuit, and a predetermined stimuli or a pseudorandom stimuli during scan-test and self-test, respectively, is shifted serially through the scan chains to all scan cells in the scan-based integrated circuit. During the capture operation, the scan enable (SE) signals are used to select the data inputs as the input source for all scan cells, to test the functional path of the scan-based integrated circuit using the stimulus loaded during the shift operation.
Automatic test pattern generation (ATPG) in conjunction to fault simulation are used to generate the scan data patterns to test faults in the scan-based integrated circuit, and to measure the fault coverage of the scan data patterns during scan-test. Fault simulation is also used independently to measure the fault coverage of pseudorandom stimuli during self-test. Faults tested include stuck-at faults, transition faults either launched from shift or launched from capture, path-delay faults either launched from shift or launched from capture, IDDQ (IDD quiescent current) faults, and bridging faults. In order to simplify the ATPG and fault simulation process, a cycle-based logic simulator, as opposed to a full timing logic simulator, is embedded within the ATPG and fault simulation engine, which is used to perform the logic simulation of the capture operation during scan-test or self-test. Since the clock skew between different clock domains can vary greatly, it makes it unfeasible to try to apply the clocks of different clock domains simultaneously during the capture operation, since the clock skew between the different clock domains would result in incorrect values being simulated by the cycle-based simulator when compared to results in the actual scan-based integrated circuit. Different approaches for applying the clocks during the capture operation have been developed in order to solve this problem.
Prior-art solution #1, see FIG. 2, is the one-hot approach. In this approach, only one clock is applied during any given capture operation. This clock is used to test the intra-clock-domain combinational logic originating and terminating within the clock domain of the given capture clock, as well as the inter-clock-domain combinational logic terminating in the clock domain of the given capture clock. The advantage of this approach is that by limiting the number of clocks applied during each capture operation to only one clock, the effects of clock skew between the different clock domains cannot negatively affect the results of the cycle-based logic simulator. The disadvantage of this approach is that only a small subset of the combinational logic that exists in a scan-based integrated circuit is tested during a single capture operation, which results in a large number of capture operations, requiring a large number of scan data patterns, being generated to test the complete scan-based integrated circuit.
Prior-art solution #2, see FIG. 3, is the staggered clock approach using multi-cycle simulation. In this approach, all the clocks are applied sequentially during every capture operation. A multi-cycle logic simulator is used to perform the logic simulation of the capture operation in order to be able to perform the ATPG and fault simulation of the staggered clocks. This allows us to test all intra-clock-domain combinational logic and inter-clock-domain combinational logic of the scan-based integrated circuit. The advantage of this approach is that by staggering the clocks and using a multi-cycle logic simulator, the effects of clock skew between the different clock domains cannot negatively affect the results of the multi-cycle logic simulator. A further advantage versus the one-hot approach is that all combinational logic is tested during each capture operation, which reduces the number of scan data patterns generated to test the scan-based integrated circuit. The disadvantage of this approach is that the complexity of the ATPG and fault simulation increases due to the multi-cycle logic simulator. This also increases the amount of time required to generate and fault grade the scan data patterns. Other variations of this approach also exist, where only a limited number of clocks are applied during each capture operation.
Prior-art solution #3, see FIG. 4, is the staggered clock approach using the circuit expansion approach proposed in the U.S. Patent Application 20020184560 by Wang et al. (2002). In this approach, all the clocks are applied sequentially during every capture operation. Circuit expansion is used to create a new circuit model where all clocks are applied simultaneously during the capture operation, while modeling the results of the logic simulation of the original circuit where all clocks are applied sequentially during the capture operation. This allows us to test all intra-clock-domain combinational logic and inter-clock-domain combinational logic of the scan-based integrated circuit. The advantage of this approach is that by performing circuit expansion, a simple ATPG and fault simulation engine can be used to generate and fault grade the scan data patterns while preventing the effects of clock skew between the different clock domains from negatively affect the results of the cycle-based logic simulator. A further advantage versus the one-hot approach is that all combinational logic is tested during each capture operation, which reduces the number of scan data patterns generated to test the scan-based integrated circuit. The disadvantage of this approach is that the circuit expansion results in a larger memory space requirement for the ATPG and fault simulation tool. Furthermore, the depth of the logic cone increases for clocks that are applied later in the capture operation, which increases the time it takes to generate and fault grade the scan data patterns for these clocks. This can also result in some faults becoming untestable due to the amount of backtracks required to search the depth of the expanded logic cones to find a pattern. Other variations of this approach also exist, where only a limited number of clocks are applied during each capture operation.
Prior-art solution #4, see FIG. 5, is the staggered clock approach using the primary capture event approach described in U.S. Pat. No. 6,195,776 by Ruiz et al. (2001). In this approach, all the clocks are applied sequentially during every capture operation. A selected clock is designated as the primary capture event (PCE) and all clocks are applied simultaneously during the capture operation simulation. A cycle-based logic simulator is used to perform a logic simulation with respect to the PCE clock. In order to guarantee that the cycle-based logic simulator can accurately predict the results in the actual scan-based integrated circuit where clocks are applied sequentially, all scan cells are analyzed with respect to the PCE clock to determine whether they can be controlled and observed at the time of the primary capture event. Scan cells that are driven by the PCE clock are labeled as both controllable and observable. Scan cells driven by clocks that are applied before the PCE clock are labeled as uncontrollable, since their value cannot be predicted at the time of the primary capture event. Scan cells driven by clocks that are applied after the PCE clock are labeled as unobservable, since the values captured into these storage elements cannot be correctly determined at the time of the primary capture event.
The advantage of this approach is that by selecting a PCE clock and labeling scan cells as controllable and/or observable with respect to the primary capture event, a simple ATPG and fault simulation engine can be used to generate and fault grade the scan data patterns while preventing the effects of clock skew between the different clock domains from negatively affect the results of the cycle-based logic simulator. A further advantage versus the multi-cycle simulation and circuit expansion approaches is that this approach does not require any additional complexity or memory space. The disadvantage of this approach is that only a subset of the inter-clock-domain combinational logic is tested during any given capture operation, which increases the number of scan data patterns when compared to the multi-cycle simulation and circuit expansion approaches. A further disadvantage is that a larger number of expected unknown (‘x’) values can be generated, which can create difficulties for existing scan compression solutions. Other variations of this approach also exist, where only a limited number of clocks are applied during each capture operation.
Reference is made to the following: